STA Synthesis (sta/constraints)

STA Synthesis (sta/constraints)

Location:- Bangalore

Experience:- 7+Years

Job Purpose

As an engineer, Timing Closure, and Constraints Coding/Validation Engineer, you will own the architectural timing intent, constraint hygiene, and complete timing sign-off for complex, multi-million gate SoCs. You will drive multi-mode multi-corner (MMMC) timing closure from block-level implementation up to full-chip integration. A core focus of this role is using advanced optimization tools to fix critical setup, hold, transition and crosstalk violations across both functional and complex DFT modes (Scan, At-Speed, MBIST etc).

 

Key Responsibilities

• Timing Closure & ECO Sign-off:  Lead and execute block-level and full-chip flat/hierarchical timing closure across advanced process nodes. Generate engineering change orders (ECOs) to fix setup, hold, max transition, and signal integrity violations.
• Tool-Driven Optimization:  Demonstrate expert mastery over automated ECO fixing tools ( Tweaker, PT DMSA/Primeclosure, Cadence Tempus)  drive rapid convergence of complex bottleneck violations.
• Multi-Signoff STA Infrastructure:  Architect, set up, and execute robust MMMC sign-off environments using  Synopsys PrimeTime (PT/PT-PX)  and  Cadence Tempus . Ensure complete correlation across different timing engines.
• Hierarchical Constraint Management:  Architect, generate, and maintain clean SDC files at both the Block/IP level and the Full-Chip Top level. Manage constraint promotion, demotion, and validation.
• Signal Integrity & Noise Analysis:  Strong understanding of crosstalk-induced noise, glitch propagation, signal electromigration (Signal EM), and managing  reconvergent timing paths  affected by crosstalk delay
• DFT Mode Timing Validation:  Define, audit, and validate constraints across multiple operational modes, specifically targeting Scan Shift & Capture, At-Speed Testing, Memory BIST (MBIST), and Logic BIST (LBIST) concurrent execution modes.
• Cross-Functional Leadership:  Collaborate with DFT Engineers to resolve test mode constraints, RTL Designers to fix structural CDC/RDC violations, and P&R Teams to guide placement, clock-tree synthesis (CTS), and routing optimizations.
• Automation & Flow Development:  Write advanced, production-grade  Tcl scripts  for PrimeTime/Tempus environments. Utilize  Python  or  Perl  to build regression suites, analyze timing violations, and compare SDC variations.

 

Required Technical Skills & Qualifications

• Education:  Bachelor’s or Master’s degree in Electrical/Electronics Engineering, VLSI, Microelectronics, or a related field.
• Core Tool Expertise (Mandatory):
  • Sign-off STA:   Synopsys PrimeTime (PT/PT-PX)  and  Cadence Tempus .
  • Timing Closure / ECO:   Cadence Tempus, Synopsys PrimeTime/PrimeClosure & Tweaker .
  • Constraints Validation:   Synopsys TCM/GCA ,  Ausdia TimeVision ,  SpyGlass Constraints , or  Cadence CCD .
• Methodologies:  Deep understanding of advanced node variation models (POCV/LVF), temperature inversion, crosstalk/noise analysis, and hierarchical top-level clock distribution networks.
• DFT Concepts:  Solid comprehension of DFT architecture, test clock structures, multiplexer-heavy clock networks, and asynchronously driven test logic.
• Scripting Capabilities:  Expert proficiency in  Tcl  (highly critical for runtime timing script customization) and  Python/Perl  for automated data mining and constraint auditing.

 

Good to have skills

• Constraint validation:  Run strict constraints verification using industry-standard tools ( Synopsys TCM ,  SpyGlass Constraints , or  Cadence CCD ) to eliminate unconstrained paths, incorrect clock-gating checks, and conflicting case analysis settings between functional and DFT modes
• Power-Aware Verification (UPF):  Hands-on experience reading, writing, and parsing  Unified Power Format (UPF)  constraints to validate low-power design architectures (e.g., power-gating, isolation cells, retention registers, and level-shifter placement)
• Formal Verification (LEC): Familiarity with Logic Equivalency Checking using industry tools like  Cadence Conformal LEC  or  Synopsys Formality  to verify that optimization/ECO steps maintain functional equivalence 

 

Soft Skills & Interpersonal Attributes

 

• Proactive Leadership ("Step Up"):  Demonstrated ability to  step up  and take full ownership of critical, high-stakes tape-out blockers. Act as a self-starter who proactively anticipates timing risks before they impact scheduling.
• Collaborative Team Player:  A strong  team player  who can easily collaborate across diverse, multi-functional engineering teams (RTL, DFT, P&R) to resolve conflicting constraints and drive common goals.
• Analytical Debugging:  Exceptional debugging and analytical skills to isolate root-cause issues in complex multi-mode SDC and timing reports.
• Strong communication and technical leadership skills to drive timing convergence across global implementation teams.
• Exceptional debugging and analytical skills to isolate root-cause issues in complex multi-mode SDC and timing reports.