RTL Design - 7+yrs

Your Role

Key responsibilities in your new role
 

• Develop micro-architecture and RTL coding for IP development in system Verilog/Verilog
• Work with the stakeholders and manage the digital IP roadmap
• Perform comprehensive quality checks to ensure robustness and accuracy of IP design including Lint, CDC, RDC, synthesis, DFT checks, ATPG
• Put strong processes in place to ensure no bugs escape from IP qualification flow
• Technically lead and mentor the juniors working with you

 

Your Profile

Qualifications and skills to help you succeed
 

• Bachelor’s or master’s degree in electrical or Electronics Engineering
• 7+ years of experience in semiconductor Digital IP development, with demonstrated leadership within your area of expertise
• Proven experience in digital IP RTL development
• Experience IO controller design will be an added advantage
• Knowledge of commonly used bus protocols like AHB/APB is a must
• Proven technical leadership skills in driving IP roadmaps with stakeholders
• Strong debugging skills for resolving integration-level issues and system level issues
• Proficiency in System Verilog, Verilog
• Experience working with automated flows for generating RTL, along with the ability to enhance these workflows through scripting
• Familiarity with leveraging AI tools to optimize and improve RTL integration workflows
• Experience in managing RTL releases and handling release containers Proactive and collaborative approach to risk identification and mitigation, with excellent communication and presentation skills
• Ability to thrive in a fast-paced, global environment, collaborating with cross-functional teams including Architecture, IP, Physical Design, Verification, and DFX
• Working knowledge of UNIX and Windows environments, along with MS Office tools (PowerPoint, Excel) and version control systems such as Git
• Proficiency in scripting languages, particularly Python