Director Digital Design Verification

Your Role

Key responsibilities in your new role
 

• Drive Digital mixed Signal Verification of Complex Signal processing IPs and chips
• Enable AI in Verification
• Technical guidance and career mentorship to the team
• Lead from the front
• Hands-on experience building Simulink models that correlate to fixed-point hardware implementations (bit-accurate or tolerance-defined reference models).
• Experience collaborating with RTL design and DV teams (UVM/scoreboards/reference models), driving requirements-to-implementation traceability.
• Ability to interpret and integrate analog collateral (ADC behaviour, trims/calibration, validity timing, comparators/monitors) into digital models and verification plans.
• Strong system-thinking and ownership mindset; comfortable leading cross-team technical decisions and driving signoff-quality closure.
• Power converter control experience (multi-phase regulation, current sharing, transient optimization) is highly desired
• Mixed-signal verification exposure (co-simulation workflows, model correlation).

 

Your Profile

Qualifications and skills to help you succeed

 

• System modelling & specification: Build end-to-end behavioural models (plant + sensing + digital control + telemetry), define measurable requirements (stability, transient response, accuracy, latency), and translate them into implementable specs.
• Filter/algorithm implementation alignment: Own the modelling and fixed-point specification of key digital signal-processing elements (moving averages, programmable IIR poles/compensators, notch/CIC-style filters, envelope/marker capture, scaling/formatting), and work with RTL designers to ensure faithful implementation.
• Strong background in discrete-time filter design and fixed-point DSP implementation (IIR/PID, rounding/saturation behaviour, coefficient quantization, numeric stability).
• Cross-functional integration: Act as the technical interface between analog and digital teams; Define analog collateral (ADC behaviour, sampling/validity timing, trims/calibration, comparators/monitors) and ensure consistent assumptions in models, RTL, and verification.
• Verification strategy & closure: Define multi-level verification strategy (math-block golden models → subsystem digital verification →mixed-signal validation → full-chip end-to-end scenarios) and drive closure with verification leads.
• Bring-up & debug readiness: Define bring-up checklists, debug observability requirements, and lab validation plans; support root-cause analysis across RTL, firmware, and bench data.
• Documentation & leadership: Own technical collateral (architecture, modelling assumptions, coefficient derivations, fixed-point formats, test plans) and lead design/verification reviews.