Sr. Staff Engineer – Static Timing Analysis (STA)

Bengaluru, Karnataka, India25 Jun 2026RY3TXU

mediatek/sr-staff-engineer-static-timing-analysis-sta

Sr. Staff Engineer – Static Timing Analysis (STA)

Job Description

NOTE- KINDLY UPDATE YOUR CV WITH KEY SKILLS HIGHLIGHTED IN JD,

NOTICE PERIOD SHOULD BE LESS THEN 2 MTH.

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ctc- fixed+variable+rsu for years,

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notice period-

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Sr. Staff Engineer – Static Timing Analysis (STA) |

We're seeking an experienced Lead Engineer for a Timing Leadership role, ready to drive innovation and excellence in advanced process nodes (6 nm and below). As the STA Lead, you will ensure our high-performance designs achieve their timing, power, and schedule targets, while fostering a culture of critical thinking and innovation.

Job Responsibilities:

Lead the team through the full STA cycle, from initial constraints validation to final GDS sign-off
Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage SoC and subsystem designs
Manage timing ECOs (DMSA, tweaker, PrimeClosure) and conduct logical equivalence checks (RTL to Netlist)
Validate and debug timing across multiple PVT conditions using tools such as PrimeTime and Tempus
Work closely with RTL, Synthesis, and Physical Design teams to influence floorplanning and CTS strategies for timing-optimized layouts
Partner with design, DFT, synthesis, technology, CAD, and physical implementation teams
Collaborate with Project Leaders to create schedules, track progress, and raise issues or risks to project management

Required Skills:

10+ years of relevant experience in STA and semiconductor design
Proven experience in driving timing convergence at chip-level and hard macro level
Strong expertise in STA fundamentals, AOCV/POCV concepts, CTS, and timing constraints
Hands-on experience with STA tools: PrimeTime, Tempus, Tweaker
Familiarity with ASIC back-end flows such as ICC2 and Innovus
Experience in low-power synthesis and equivalence checks is a plus
Exposure to RTL-to-GDSII desig n flows
Knowledgeable in clock gating, power gating, and multi-voltage design techniques
Understanding of signal integrity, crosstalk noise, and parasitic extraction
Proficient in scripting languages: TCL, Perl, and Python
Experience mentoring junior engineers in timing flows and methodologies
Well organized, methodical, and detail-oriented
Involved in high-speed design tape-outs and constraint development across multiple modes

Quick Apply

~2 min

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CompanyMediaTek

Departmenttechnology

Posted25 Jun 2026