Staff/Sr.Staff Design Engineer

Send the profile 12 to 18Yrs exp

Please support this role.

As a Staff/Sr.Staff Design Engineer, your job will entail the following:

• Design planning of pad rings and package substrates, bump pattern construction.
• Dynamically define and optimize pad ring connectivity.
• Work with CFTs (Cross-Functional Team) on the deliverables (DEF, Verilog netlist etc.,)
• Interface with and support Architect, PD, PE, technology development and foundries teams.
• Support JTAG TAP controller integration and implementation across SoC designs, ensuring IEEE 1149.1 compliance and proper JTAG signal connectivity in collaboration with the DFT team.
• Collaborate with CFTs on TAP controller operation, scan-enable path handling, and post-silicon debug requirements.
• Support Verification, Emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds.

• Covercell design enabling SOC implementation and package development:
   
• Experience in implementing and managing covercells with:
   
• various IO cells (GPIO, I2C/I3C, LVDS and others)
   
• standard hard macros including DDR, PCIe, Serdes, Ethernet
   
• custom in-house hard macros
   
• Understanding of chip BGA package related data like die text, bump to ball, package routing constraints
   
• IORing Signoff
   

- Understanding and management of signoff including:
 

• Bump rules drc checks
   
• SOC ESD and Latchup in advanced Foundry nodes