Senior Engineer-I Design Implementation-STA

Microchip-Bangalore                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       Senior Engineer-I Design Implementation                                                                                                                                                                                                                      Job Description:
Microchip Technology Inc. is looking for an experienced engineer to work in a team that is responsible for doing Design Implementation (Synthesis/STA/Timing closure/Formal Equivalence) of 32-bit Microcontroller based products. The role will include optimizing PPA (Power/Performance/Area) metrics during synthesis and performing static timing analysis, design verification/signoff using an industry leading design implementation flow.

Job Requirements:
Key Responsibilities:
* Evaluate new tools/features, develop and maintain flows.
* Execute Synthesis, Formal equivalence, Low Power Checks and Static Timing Analysis using the tools and flows for Microchip’s 32-bit microcontroller product lines.
* Drive collaterals generation and management, SoC timing budgeting, constraint analysis, optimization, and sign-off timing/power closure.
* Work alongside architecture, design, verification and physical design teams to support constraint and UPF development, timing debug/fixing and support gate level simulations.
* Participate in SoC development planning and scheduling.
* Continuously improve RTL-to-Netlist tool flows and methodologies.
* Interact with tool vendors and debug tool related or IP related issues

Requirements/Qualifications:
* BSEE minimum, MSEE preferred
* Minimum 3 to 4 years of relevant experience
* Good exposure to RTL2GDS flow for digital and mixed signal designs. Hands-on experience with STA, Synthesis, UPF and Functional equivalence. The ability to implement power constraints using UPF/CPF constructs is a plus.
* Design flow development experience using scripting (TCL/Perl/Python) languages.
* Good documentation and presentation skills.
* Demonstrated ability to interact and collaborate well with other team members in a cross functional and cross site team environment.
Travel Time: 0% - 25%