Principal engineer- RTL Design

• - RTL Design Engineer – MTS (12 – 18 yrs exp) – 
• Location-Hyderabad:

Job Description

Responsibilities will include, but are not limited to:

Contribute to the Development of New Memory Products by owning the overall logic design of the on-chip memory controller, including all optimizations and pathfinding.

• Responsible for meeting the performance/area/power targets
• Ability to interpret device and system specifications to produce required functionality
• Participate in new circuit conception and design as needed
• Define and build design architecture spec documents for the new features
• Assist in design and development of schematics and/or RTL blocks

Lead and Develop Projects and Team (Leads)

• Plan and prioritize projects and resource requirements, including planning, and scheduling activities and tasks, and management of designers wrt all new requests
• Serve as main point of contact for communication for Logic design and development for the NAND product
• Track progress, supervise when items are completed and what still needs to be done
• Prepare project status reports for upper management
• Plan and hold code reviews to discuss progress and decisions made about project
• Mentor new hires and supervise progress
• Build training programs for ramping up team members

Maintain Technical Expertise and provide training

• Define best known design and verification practices and communicate to the entire department
• Prepare detailed documentation as the need arises
• Participate in recruiting, and interviewing new candidates
• Build new hire ramp up plans
• Engage in continuing education and competitor analysis

Manage Verification Processes

• Perform RTL and synthesized netlist (gate level) verification at block, subsystem, and fullchip level
• Facilitate netlist bring up to achieve basic functionality
• Responsible for delivering design simulation including post layout
• Create verification plan for new and existing features and check encouraged behavior in Verilog
• Collaborate with Product Engineering wrt validation plan and review Silicon result
• Assist in silicon design validation, reticle experiments, qual and tape-out revisions as needed

 

Contribute to Cross Group Communication to Work Towards Standardization and Group Success

• Work with Device, System, Probe, Test, CAD, Field Application Engineers, and Product Engineering groups to ensure accurate manufacturability of product
• Proactively solicit mentorship from various groups (i.e. Standard cell development, simulation, voltage)
• Additional Job Description

Additional Job Description

Qualifications and Skills include, but not limited to:

• 10+ years of experience
• MS degree or BS in Electrical engineering or Computer Sciences is required.
• Proven knowledge of CMOS Circuit Design
• Experience in RTL design, design synthesis, static timing analysis, and automated layout techniques
• Hands-on experience with verilog modeling and simulation tools
• Knowledge of state machine logic/design verification techniques
• Excellent problem-solving and analytical skills
• Knowledge and/or experience in non-volatile memory design (NAND in Particular) is required.
• Good Understanding of large-scale design projects is desirable.
• Knowledge of Digital ASIC Design Methodology is required.
• Experience with Mixed-Mode design and validation is a Plus.
• Hands-on experience with Design/Verification CAD Tools such as ncsim, Design compiler, Formality, PrimeTime, etc.
• Experience with transistor level simulators such as Spice, Ultrasim, and HSIM is desirable.
• Knowledge of TCL, PERL or Python preferred.
• Ability to establish and maintain good relationships with colleagues.
• Self-Motivated, self-directed, and a phenomenal teammate (on the same team and outside of the team).