Analog Design Engineer

  Analog Design Engineer 

• Location:- Bangalore

  Experience:- 7+Years

  Job Description

  Our vision is to transform how the world uses information to enrich life.

  Join an inclusive team focused on one thing: using their expertise in the steadfast pursuit of innovation for customers and partners. The solution we create help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing!

  Position Description:

  To be part of a highly skilled and challenging high speed PHY build team working on the newest technology nodes (12nm and below).

  Take ownership of analog sub-blocks inside the PHY and drive the specification and implementation. It includes transistor and block level design, simulation, reliability and mixed mode simulations etc.

  Leverage AI-enabled tools to improve productivity and decision making.

  Drive layout of sophisticated blocks through mask designers. Conform to complex process rules as well as DFM or equivalent experience.

  Participate in design reviews both internally and potentially with customers to explain design choices and robustness. Work with people across multiple sites including overseas.

  Help with creating IP EDA views: Behavioral/Verilog-A, timing views, abstract etc.

  Participate in silicon bring up, characterization, & perform correlations against models & simulations.

  Mentor and supervise entry-level engineers.

  Equal opportunity position with excellent pay package!

  SKILLS required:

  Circuit design experience in analog/mixed signal CMOS circuits in deep sub-micron technologies (2 – 28 nm) in High speed Memory interfaces (DDR3/4/5, LPDDR5/6, GDDR5/6/7) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA etc).

  Prior experience in taking full ownership of at least on of the sub-blocks like PLL, DLL, CDR, high speed receiver with equalization, transmitter front end and high speed data path.

  The candidate is encouraged to possess a deep understanding of analog and mixed signal circuits along with experience in high speed link.

  Candidate must have experience in Serdes/Parallel Interface.

  Experience with TX RX Equalization (FFE/CTLE/DFE) is must

  Experience with various CDR and Clocking architecture.

  Candidate should have experience in finfet 10nm and below.

  Able to create block level specification based on link budget.

  Able to create system level modeling using VerilogA/Python.

  Should be able to work with Packaging/Board team.

  Should have knowledge of ESD.

  Experience in lab testing and work with validation team to analysis data.

  High speed I/O cell designs such as DDR, LVDS, HSTL, CML.

  Power Delivery circuits such as Bandgap, LDO , Bias circuits.

  Strong fundamental knowledge for AMS design, Advanced CMOS and FinFet technologies.

  Understanding of Mismatch analysis & Monte-Carlo methodology/sims, transistor level Circuit level noise analysis. Understanding of device physics & deep-sub micron issues.

  Supervision of complex and/or critical analog layout and defining IP floorplan

  Experience with industry standard tools such as Cadence ADE, Spectre, AMS verification, EM/IR flows, MATLAB, Calibre etc.

  Working knowledge of Mixed mode simulation, Signal Integrity and ESD desired.

  M.S./M.Tech, BS/BE (Electronics)

  Experience Required : 7+ Years

• Additional Job Description

  Leads all aspects of definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.