Job Description
Location:- Hyderabad
Experience:- 9+Years
Responsibilities will include, but are not limited to:
Contribute to the Development of New Memory Products by owning the overall
logic design of the on-chip memory controller, including all optimizations
and pathfinding.
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Responsible for meeting the performance/area/power targets
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Ability to interpret device and system specifications to produce required
functionality
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Participate in new circuit conception and design as needed
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Define and build design architecture spec documents for the new features
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Assist in design and development of schematics and/or RTL blocks
Lead and Develop Projects and Team (Leads)
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Plan and prioritize projects and resource requirements, including planning,
and scheduling activities and tasks, and management of designers wrt all new
requests
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Serve as main point of contact for communication for Logic design and
development for the NAND product
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Track progress, supervise when items are completed and what still needs to
be done
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Prepare project status reports for upper management
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Plan and hold code reviews to discuss progress and decisions made about
project
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Mentor new hires and supervise progress
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Build training programs for ramping up team members
Maintain Technical Expertise and provide training
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Define best known design and verification practices and communicate to the
entire department
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Prepare detailed documentation as the need arises
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Participate in recruiting, and interviewing new candidates
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Build new hire ramp up plans
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Engage in continuing education and competitor analysis
Manage Verification Processes
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Perform RTL and synthesized netlist (gate level) verification at block,
subsystem, and fullchip level
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Facilitate netlist bring up to achieve basic functionality
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Responsible for delivering design simulation including post layout
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Create verification plan for new and existing features and check encouraged
behavior in Verilog
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Collaborate with Product Engineering wrt validation plan and review Silicon
result
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Assist in silicon design validation, reticle experiments, qual and tape-out
revisions as needed
Contribute to Cross Group Communication to Work Towards Standardization and
Group Success
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Work with Device, System, Probe, Test, CAD, Field Application Engineers, and
Product Engineering groups to ensure accurate manufacturability of product
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Proactively solicit mentorship from various groups (i.e. Standard cell
development, simulation, voltage)
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Additional Job Description
Additional Job Description
Qualifications and Skills include, but not limited to:
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10+ years of experience
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MS degree or BS in Electrical engineering or Computer Sciences is required.
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Proven knowledge of CMOS Circuit Design
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Experience in RTL design, design synthesis, static timing analysis, and
automated layout techniques
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Hands-on experience with verilog modeling and simulation tools
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Knowledge of state machine logic/design verification techniques
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Excellent problem-solving and analytical skills
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Knowledge and/or experience in non-volatile memory design (NAND in
Particular) is required.
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Good Understanding of large-scale design projects is desirable.
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Knowledge of Digital ASIC Design Methodology is required.
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Experience with Mixed-Mode design and validation is a Plus.
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Hands-on experience with Design/Verification CAD Tools such as ncsim, Design
compiler, Formality, PrimeTime, etc.
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Experience with transistor level simulators such as Spice, Ultrasim, and
HSIM is desirable.
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Knowledge of TCL, PERL or Python preferred.
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Ability to establish and maintain good relationships with colleagues.
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Self-Motivated, self-directed, and a phenomenal teammate (on the same team
and outside of the team).
Principal Design Verification : 10+ yrs experience - Hyderabad
Job Description
Responsibilities include, but not limited to:
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Full-chip functional verification on Micron’s non-volatile memory design
projects
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You thoroughly understand design specs and develop verification plans for
various designs.
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Test bench Development in System Verilog targeting complete functionality
coverage.
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Support of System Verilog assertion and coverage-driven methodology
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Support of design verification methodology improvements
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Run directed and constrained-random verification tests.
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You will think through design corner cases and be able to write relevant
cover points.
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Collaborate with digital design team to debug test cases and deliver
functionally accurate designs.
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Close coverage measures to identify verification holes and to show progress
towards tape-out.
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Development of Micron’s NAND Flash behavioral models in System Verilog.
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Technical support to internal and external model users
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Complete verification on Micron’s NAND Flash models based on design
datasheet.
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Collaboration with Application engineers on design datasheet and model
requirements
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Driving innovation into the future Memory generations within a dynamic work
environment
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Additional Job Description
Additional Job Description
Minimum Qualifications:
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MS or BS degree in Electrical or Computer Engineering or equivalent
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7-15 of experience developing verification collateral in Verilog, System
Verilog and UVM
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UVM Proficiency is a must.
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Prior work experience with complex coverage driven random constraint UVM
environments.
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Putting together complex UVM environments from scratch is a requirement.
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Deep knowledge on circuit design, digital logic, and logic verification
methodology
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Understanding on Verilog RTL coding, System Verilog object-oriented language
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Good knowledge on programming language such as C++, and scripting language
like TCL and PERL
Preferred Skills:
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Knowledge of Non-volatile memory design is highly desired.
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Strong communication skills both written and verbal.
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Strong interpersonal skills and maintain positive relationships.
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Ambitious and goal oriented
Collaborate effectively in a dynamic team environment.