Techno Manager-DFT

Job Description

Location:- Bangalore

Experience:- 12+Years

About the job

We are seeking a skilled Design for Test (DFT) Principal Engineer to join our team. This role is pivotal in ensuring the testability and manufacturability of our ASIC/SoC products designed for the automotive, Industrial & Consumer applications. The ideal candidate will have extensive experience in DFT methodologies and will lead a team of engineers to develop robust test strategies that meet industry standards.

Responsibilities

Key Responsibilities:

DFT Strategy Development: Design and implement DFT methodologies for ASIC/SoC products, focusing on automotive/industrial/consumer applications to ensure high quality and reliability.

Architecture Design: Collaborate with hardware and software teams to integrate DFT features into the product architecture, ensuring compatibility with testing standards.

Team Leadership: Lead & manage a team of DFT engineers, providing mentorship and technical guidance to enhance their skills and capabilities.

Test Planning: Develop comprehensive test plans, including ATPG, BIST, and scan insertion strategies, to optimize fault coverage and reduce test costs.

Collaboration: Work closely with design, validation, test and manufacturing teams to align DFT strategies with overall product goals and requirements.

Quality Assurance: Establish metrics and benchmarks for DFT processes, and ensure compliance with automotive industry standards (e.g., ISO 26262).

Tool Development: Evaluate and implement DFT tools and methodologies to improve test efficiency and effectiveness.

Continuous Improvement: Stay updated with industry trends and technologies in DFT and automotive testing, driving innovation within the team.

Qualifications

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

12+ years of experience in DFT for ASIC/SoC design, with a strong background in automotive applications.

Proven experience leading DFT teams and managing complex projects.

Experience in post silicon debug, yield improvement and On-field failure (EFAR) debug.

In-depth knowledge of DFT techniques such as scan design, boundary scan, BIST, and fault simulation.

Familiarity with automotive industry standards and regulations (e.g., ISO 26262).

Proficiency in using DFT tools and EDA software.

Strong problem-solving skills and ability to work collaboratively in a fast-paced environment.

Excellent communication skills, both verbal and written.