Sr Principal Digital IC Verification Engineer- 13+yrs

 

  Job opening - Senior Principal Digital IC Verification Engineer. 

Exp-  13yrs

Location - Bangalore

 

Responsibilities for Internal Candidates

 

What You’ll Do 

 

• Define the verification strategy and the detailed verification plans for blocks and systems 
• Coordinate/lead the verification activities in the project teams and reach verification closure for the projects 
• Develop SystemVerilog/UVM environments for blocks and top-level SoCs 
• Debug functional errors in RTL 
• Participate to verification methodology improvement activities 
• Coach and mentor younger engineers 

 

What You’ll Need 

• Minimum BS/MS in Electrical Engineering or related technical field 
• At least 13-17 years of digital verification experience 
• Solid understanding of verification best practices such as verification planning, requirements tracking, and functional coverage 
• In-depth knowledge and some years of proven experience in state-of-the-art verification methodologies (e.g. UVM), constrained random driven verification, assertion-based verification, test environment architecture & creation, regression management, coverage collection, and formal verification 
•  

Qualifications for Internal Candidates

• Experience in technical project/task leadership 
• Excellent written and verbal communication skills in English 

What Else You May Bring  

 

• Experience in some of the following areas is a plus: 
• Experience in the verification of CPU/MCU (sub)systems, SystemRDL or IP-XACT 
• Programming in Python for automation and in C/C++ for embedded software 
• Verification of signal processing components 
• 3rd party verification IP deployment