Qualcomm_Chennai_Hardware Engineer BLR_Synthesis _13+yrs

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

 

General Summary:

Qualcomm Chennai is seeking a highly motivated  Synthesis (Design Implementation) Engineer  to drive synthesis and low-power implementation for complex SoC and subsystem designs. The candidate will work closely with Design, Physical Design, DFT, and Timing teams to achieve competitive Power, Performance, and Area (PPA) targets on advanced technology nodes.

 

Key Responsibilities

 

• Lead and manage synthesis deliverables across multiple blocks/subsystems, ensuring schedule, quality, and tape out commitments are met.
• Mentor and technically guide team members on timing closure, UPF methodologies, advanced-node implementation challenges, and debug strategies
• Drive execution reviews, risk assessment, and closure plans for project milestones.
• Coordinate across RTL, DFT, Physical Design, STA, and Verification teams to resolve cross-functional issues and improve design convergence.
• Define and drive synthesis methodologies, best practices, and flow improvements across the team.
• Contribute to resource planning, execution tracking, and prioritization of team deliverables.
• Run quality checks including  check_design, check_timing, Lint, CDC, ERC , and support MTBF-related fixes.

 

Required Skills

 

• Strong experience with physical and low-power-aware synthesis using  Synopsys Fusion Compiler/Design Compiler  or  Cadence Genus .
• Implement and validate  UPF-based low-power architectures , including isolation cells, level shifters, retention cells, and power switches
• Develop and maintain  SDC constraints , perform Pre-STA analysis, and drive pre-layout timing convergence.
• Expertise in  PrimeTime/Tempus ,  UPF ,  CLP , and  Formality/Conformal/ Conformal ECO .
• Good understanding of  multi-voltage designs , low-power methodologies, and timing closure
• Develop automation and flow improvements using  AI agents,   TCL, Perl, Python, and Shell scripting

 

Preferred Qualifications

• Experience with advanced nodes ( 6nm/5nm/4nm/3nm or equivalent ).
• Ownership of synthesis for blocks/subsystems with  2M+ cells .
• Expertise in  UPF, multi-voltage designs, POCV/AOCV,  and  variation-aware high-speed timing analysis.
• Experience with flat-level signoff flows, LEC, CLP, and physical synthesis methodologies.
• Ability to independently drive synthesis and low-power closure through tape-out
• IO timing closure

 

 

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of hardware engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.