Design Verification

DV Verification Engineer 

Location:- Bangalore  

Expereince:- 7-11years  

Requirements/Qualifications:

• BS or MS degree in electrical or computer engineering or closely related degree strongly preferred; but substantial, relevant, outstanding work experience may substitute in some cases
• Eight to Ten years of experience working as a verification engineer or related field
• Strong written and verbal communication skills: ability to explain complex concepts in front of technical audience
• Strong desire to take ownership of all verification aspects of a project, including team and methodology leadership
• Exposure to block-level and/or system-level verification
• Highly technical competence that includes a track record of effective verification of complex digital designs
• Solid understanding of standard ASIC verification techniques, including:
  • Test planning
  • Testbench creation
  • Code and functional coverage
  • Directed and SystemVerilog-based constrained random stimulus generation
  • Self-checking – scoreboards, predictors, or reference models
  • Assertions
• Solid understanding of verification methodologies (UVM or OVM) and standard testbench languages
• Comfortable with Unix development environments (make, scripting, SVN, etc.), and with industry-standard EDA tools (VCS, Xcelium)
• Ability to support testbench lint/rule checking, profiling and automation using perl or python scripting
• Familiarity with advanced verification techniques such as object-oriented testbenches, fault/stimulus injection, FPGA prototyping and/or formal verification
• Experience leading multi-site teams and projects, including task and schedule estimation
• Protocol Knowledge
  • APB, AXI and AXI Stream
  • Ethernet/MACSec and IPSec
  • Crypto-Algorithm AES,SM4 ..etc