Principal RTL Design Engineer

Principal RTL Design Engineer

Greater Noida/Bengaluru, Karnataka,                                                           Job Description

As part of the Platform design team, the Design Engineer will be responsible for leading and contributing to the design and delivery of Core Subsystem across multiple SoC generations. With deep experience in RTL design and SoC-level integration, this role is critical for enabling high-performance, low-power, and functionally safe systems across diverse markets.

Responsibilities

Collaborate with systems architects and microarchitects to define high level, implementable SOC specifications.
Own end-to-end IP/Sub-system RTL delivery while analysing and optimising design for power, performance and area (PPA) targets.
Work on IPs including ARM Cores, Interconnect Fabrics, Memory Controller IPs.
Lead RTL design and integration of Sub-system supporting complex architectures with multi-core, multi-reset domains.
Demonstrate strong proficiency with frontend flows, including LINT, CDC, Synthesis, DFT and Static Timing Analysis (STA).
Drive the development of robust Safety, Security and Debug architectures for advanced SOCs with multiple interconnects.
Design and integrate standard interface protocols like AHB/AXI and memory interfaces like RAM, Flash.
Engage cross-functionally with DFT, Physical Design, Verification, Emulation and Validation teams to ensure first time right silicon and on-time project delivery.
Support silicon bring-up, debug, and post-silicon performance analysis through detailed simulation and system-level integration.
Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle.
Utilize scripting to manage design flows and automate repetitive tasks for improved efficiency.
Mentor junior engineers, and provide technical leadership and guidance across multiple design projects.
Contribute to the innovation quotient of the team via Patents, Industry standard publications etc.

Qualifications

Bachelor's or Master’s degree or equivalent experience in Electronics/Electrical Engineering with 15+ years of RTL design experience.
Hands on experience in RTL coding, debugging, verification, synthesis and timing closure.
Strong experience in ARM based SOC architecture and ASIC design flow
AMBA protocols (AXI, AHB, APB), clock/reset domains and memory sub-systems.
Experience with EDA tools for synthesis, LINT, CDC, RDC and timing analysis.
Familiarity with formal verification techniques, static/dynamic power checks.
Proficiency in scripting and automation using Python.
Excellent leadership, communication skills.
Experience working with global cross-functional teams.
Working knowledge of safety-critical design flows in automotive systems. Knowledge of Automotive Functional Safety ISO26262 is a plus.